The present invention relates to a programmable logic array having an AC testing circuit.
Programmable logic arrays (hereinafter referred to as PLAs) known in the art may be typified by an AND and fixed-OR type PLA. This type of PLA includes, for example, three input terminals and input lines which are individually connected to the input terminals. Other input lines are individually connected to the input terminals via inverters. Two product term lines are each connected to a DC power source via an exclusive pull-up resistor. Twelve floating MOS FETs (hereinafter referred to as FAMOSes), for example, are each connected at a drain thereof to a product term lines, at a gate thereof to an input line, and at a source thereof to ground. An OR gate is connected at its output terminal to an output terminal of the PLA. Sense amplifiers are each connected between a respective one of the product term lines and a respective one of the input terminals of the OR gate. Further, two N-channel MOS FETs (hereinafter referred to as NMOSFETs) for selecting the product term lines are each connected at a drain thereof to a program circuit, at a gate thereof to a Y decoder, and at a source thereof to a respective one of the product term lines.
With a PLA having the above construction, the logic of a PLA AND array is defined by selectively programming the various FAMOSes i.e., by maintaining particular FAMOSes in a constant OFF state, as is well known in the art. With the resulting AND array logic, the PLA performs predetermined operations with signals appearing on the respective input terminals and produces the result of these operations via the output terminal.
A problem with the prior art PLA is as follows. For example, in an initial condition of such a PLA immediately after the fabrication, none of the FAMOSes has been programmed. When a signal having a high level or a low level is applied to the input terminals of the PLA, the FAMOSes connected to the product term lines become ON. Hence, the product term lines are constantly maintained at ground potential, i.e. low level. It is impossible, therefore, to measure an input-to-output delay characteristic and other AC characteristics of the PLA by applying a periodic pulse signal, for example, to the input terminals.